Generally, in a semiconductor integrated circuit, desirable voltages other than power supply voltages are internally generated by a voltage generating circuit. The generated internal voltages are used in analog circuits such as a current source, a sense amplifier, and a different voltage generating circuit. In order to minimize a variation of the voltage generated by the voltage generating circuit, the output of the voltage generating circuit is typically connected to one end of a stabilization capacitance.
Such a configuration is described in Japanese Patent Application Publications (JP-P2002-111470A, JP-P2003-22697A, JP-P2005-6489A, JP-P2004-220759A, JP-P2002-208275A, and JP-P2004-259318A).
In the Japanese Patent Application Publication (JP-P2002-111470A), a semiconductor chip includes a plurality of circuit blocks whose operational power supply voltages are different from each other and whose logic threshold voltages are substantially common. In the circuit block, a potential difference between a low potential level and a high potential level is used as the operational power supply voltage, and the logic threshold voltage is put between them. Then, a signal of amplitude corresponding to the operational power supply voltage can be outputted, and a signal of different amplitude in which the logic threshold voltage is put between them can be inputted.
In the Japanese Patent Application Publication (JP-P2003-22697A), a load circuit performs an operation in response to an activation of a control signal. An internal power supply node is connected to the load circuit. An external power supply node supplies an external power supply voltage. An internal power supply voltage generator converts the external power supply voltage into an internal power supply voltage and supplies to the internal power supply node. An excessively charging preventing section prevents the excessive charging to the internal power supply node.
In the Japanese Patent Application Publication (JP-P2005-6489A), a first transistor of a first conductive type is connected between a reference voltage node to which a predetermined voltage is applied and a first internal node, and its control electrode is connected to a second internal node. A second transistor of the first conductive type is connected between the reference voltage node and the second internal node, and its control electrode is connected to the first internal node. A first capacitance element is connected between a first input node for receiving a first control signal for pre-charging and the first internal node. A second capacitance element is connected between a second input node for receiving a second control signal for accumulating charges and the second internal node. A third transistor of a second conductive type is connected between the second internal node and an output node, and its control electrode is connected to a third internal node. A third capacitance element is connected between the third internal node and a third input node for receiving a third control signal for transferring the charges. A fourth transistor of the second conductive type is connected between the output node and the third internal node, and its control electrode is connected to the second internal node.
In the Japanese Patent Application Publication (JP-P2004-220759A), a semiconductor memory device includes a first magneto-resistance element and a second magneto-resistance element, which have tunnel magneto-resistance effects, respectively, and hold data opposite to each other; and at least one or more transfer gates. In a magnetic memory cell, those first and second magneto-resistance elements are provided in series between both ends, and at least one or more above transfer gates are connected in series to the first and second magneto-resistance elements. First and second bit lines are connected to both ends of the magnetic memory cell, respectively. A first word line for write is arranged in the magnetic memory cell. A third bit line for reading data is connected to the magnetic memory cell. A second word line for reading is connected to gate electrodes of at least one or more above transfer gates.
In the Japanese Patent Application Publication (JP-P2002-208275A), a semiconductor integrated circuit contains a function circuit and a power supply circuit for supplying at least one kind of a power supply voltage to the function circuit. Resistance elements are collectively arranged in the output unit of at least one kind of the power supply voltage, among the power supply voltages.
In the Japanese Patent Application Publication (JP-P2004-259318A), a synchronous semiconductor memory device operates as a static type memory in a pseudo manner. A plurality of dynamic type memory cells are arranged in a matrix. A signal input circuit latches an operational control signal from outside synchronously with a clock signal, and generates an internal operation instruction signal. A row selecting circuit selects a row of the memory cells in accordance with an external row address signal at a time of activation. A column circuit selects a column of the memory cells in accordance with an external column address signal at the time of activation and carries out a data access to the selected column. A control circuit sequentially activates and deactivates the row selecting circuit and the column circuit in a predetermined sequence in accordance with a first internal operation instruction signal from the signal input circuit. Also, the control circuit inhibits the deactivation of the row selecting circuit and keeps the row selecting circuit active, in accordance with a second internal operation instruction signal from the signal input circuit. Also, the control circuit further deactivates the row selecting circuit, which is kept active, in accordance with a third internal operation instruction signal from the signal input circuit.
For example, in FIG. 1A and FIG. 1B, a voltage generating circuit 101 supplies an internal voltage to a function circuit 102. A control signal generating circuit 105 outputs a signal for controlling the function circuit 102. One end of a stabilization capacitance 103 is connected to a node N1 between the voltage generating circuit 101 and the function circuit 102. Also, the other end of the stabilization capacitance 103 is connected to a terminal of a power supply voltage Vdd (FIG. 1A) or a terminal of a ground GND (FIG. 1B).
The thus-generated predetermined voltage is used as a reference voltage at a time of write or read in the semiconductor storage device. For example, in case of a magnetic random access memory (MRAM) (refer to Japanese Patent Application Publication (JP-P2004-220759A)) that has been noted from the viewpoint of a non-volatile property, a high speed operation, a large capacity and a low electric power consumption, the predetermined voltage generated by the voltage generating circuit is used to generate a write current and a read current. In particular, a high precision is required for the write current of the MRAM. Thus, the voltage variation is required to be minimized.
The voltage stabilizing technique in the semiconductor integrated circuit device (MRAM) of the related art will be further described below. Here, the explanation with regard to the generation of the write current is carried out, and the explanation with regard to the read current is omitted.
FIG. 2 is a block diagram showing the configuration of the related-art MRAM. This MRAM contains a memory cell array 110, an X-side constant current source circuit 120, an X-side selector 121, an X-side current termination circuit 122, a Y-side constant current source circuit 130, a Y-side selector 131, a Y-side current termination circuit 132 and a sense amplifier circuit 133. Moreover, the MRAM contains the voltage generating circuit 101, the stabilization capacitance 103 and the control signal generating circuit 105 that are shown in FIG. 1A. In this case, the X-side constant current source circuit 120 or the Y-side constant current source circuit 130 corresponds to the function circuit 102, and this operates in accordance with the voltage generated by the voltage generating circuit 101. The stabilization capacitance 103 is provided in parallel between the voltage generating circuit 101 and each of the current source circuits 120 and 130. The control signal generating circuit 105 supplies a decoder activation signal XDENW to the X-side selector 121 and the Y-side selector 131. Also, the control signal generating circuit 105 supplies a write signal WCSEN to the constant current source circuits 120 and 130. With regard to the voltage levels of the respective signals, the power supply voltage Vdd corresponds to a High level (H), and the ground GND corresponds to a Low level (L).
FIG. 3 is a circuit diagram showing a part of the configuration shown in FIG. 2 in detail. Here, for the purpose of simplification, the write circuit on the X-side will be mainly described.
The voltage generating circuit 101 generates an output voltage Vp1 (<the power supply voltage Vdd). The output of the voltage generating circuit 101 is connected through parasitic resistances r1 and r2, which are caused due to wirings, to the input of the X-side constant current source circuit 120 (hereinafter, to be referred to as a write current source). A voltage applied to the write current source 120 is assumed to be Vp2. Also, the stabilization capacitance 103 is connected to the node N1 between the voltage generating circuit 101 and the write current source 120. Its capacitance value Cp is variable depending on an application field, such as several 10 pF to several 10 nF. The stability of the voltage Vp2 is improved by this stabilization capacitance 103.
The write current source 120 has a Pch transistor (current source) MP and a switch MPS. The voltage Vp2 is applied to the gate of the Pch transistor MP. In short, the input voltage Vp2 to the write current source 120 is the gate voltage of the Pch transistor MP. When the voltage Vp2 is set such that the Pch transistor MP operates in a saturation region, the current source MP sends a write current Iw=½μpW/L(Vp2−Vtp)2 to a node NB. Here, μp is a mobility, W is a gate width, L is a gate length, and Vtp is a threshold voltage. The switch MPS is provided between the node NB and the output node NA of the write current source 120.
The output node NA in the write current source 120 is connected through the X-side selector 121 to the memory cell array 110. The X-side selector 121 activates one selection line in accordance with a logical product of the decoder activation signal XDENW and an address signal XAn. Also, when the write signal WCSEN becomes High, the switch MPS is turned on. Consequently, the write current Iw from the write current source 120 is supplied to a memory cell 111 or the vicinity thereof. The write signal WCSEN is a signal for activating the write current source 120.
In the circuit configuration shown in FIG. 3, when the input voltage Vp2 to the write current source 120 varies, the write current Iw from the write current source 120 is also largely varied. FIG. 4 shows the current variation caused when there is the voltage variation of several mV. This current variation is estimated through a SPICE simulation. From FIG. 4, it is known that the current variation of about 10% is caused by the voltage variation of 10 mV. In order to suppress such a voltage variation, the large size (the capacitance value Cp=several nF) is typically used as the stabilization capacitance 103.
The inventor of this application noted the following points. As mentioned above, by enlarging the size of the stabilization capacitance 103, it is possible to stabilize the voltage variation to some degree. However, because of the circuit operation, it is impossible to perfectly reduce the voltage variation to zero. Thus, even in case of the very small voltage variation such as about several μV, when the voltage variation is accumulated, there is a possibility that the circuit operation becomes unstable. In particular, in the MRAM, the voltage variation directly leads to the variation in the write current Iw. Therefore, the accumulated voltage variation causes erroneous write and reduces the reliability of a memory.
The accumulation of the voltage variation will be described below by referring to FIG. 3 and FIG. 5. FIG. 5 shows the decoder activation signal XDENW, the write signal WCSEN, the voltage VA of the output node NA, the voltage VB of the node NB, the gate voltage Vp2 of the Pch transistor MP (current source) and the current Ip flowing through the parasitic resistance r1. The respective signals are assumed such that the power supply voltage Vdd corresponds to the High level (H), and the ground GND corresponds to the Low level (L).
At a time of standby, namely, when the write signal WCSEN is Low, the gate voltage Vp2 of the Pch transistor MP is equal to the output voltage Vp1 (<the power supply voltage Vdd) of the voltage generating circuit 101. Also, at this time, the voltage VA is Low, and the voltage VB is High.
At a time t1, the write signal WCSEN becomes High, and the write current source 120 is activated. Then, the voltage VB of the node NB decreases sharply toward the Low level. Also, the gate voltage Vp2 decreases due to the coupling of a parasitic capacitance Cc of the current source MP. Since the gate voltage Vp2 becomes lower than the voltage level Vp1, the current Ip flows into the stabilization capacitance 103. Because of this flow-in charges, the gate voltage Vp2 is gradually increased. After the sufficient elapse of the time, the gate voltage Vp2 comes close to the voltage level Vp1.
At a time t2, the write signal WCSEN becomes Low, and the write current source 120 is deactivated. Then, the voltage of the node NB sharply returns to Vdd. Also, the gate voltage Vp2 is increased due to the coupling of the parasitic capacitance Cc. At this time, reversely, since the gate voltage Vp2 becomes higher than the voltage level Vp1, the current Ip flows out from the stabilization capacitance 103 to the voltage generating circuit 101. With the sufficient elapse of the time, the gate voltage Vp2 comes close to the voltage level Vp1.
However, as shown in FIG. 5, when a next write operation starts at a time t3 before the gate voltage Vp2 is perfectly returned to the voltage level Vp1, a problem is caused. That is, at the time t3, there is a difference between the gate voltage Vp2 and the voltage level Vp1. Thus, the write operation is carried out in the situation that the gate voltage Vp2 is beyond a design value. There is a possibility that the next write operation starts immediately after the completion of the write operation at a time t4. The repetition of such an operation results in the accumulation of the differences between the gate voltage Vp2 and the voltage level Vp1. That is, the great voltage variation is generated with regard to the gate voltage Vp2. In the case of the MRAM, the variation in the gate voltage Vp2 directly leads to the variation in the write current Iw. Thus, it becomes impossible to insure the stable write operation.
FIG. 6 shows a result of a SPICE simulation to explain the foregoing phenomenon. In FIG. 6, a longitudinal axis (Ip) shows a parasitic current that flows through the parasitic resistance r1 from the voltage generating circuit 101 to the stabilization capacitance 103. For the write period during which the write current source 120 is activated, a parasitic current Ip of about +90 μA flows. On the other hand, when the write current source 120 is deactivated, the parasitic current Ip of about 2 μA flows from the stabilization capacitance 103 to the voltage generating circuit 101. A sum of values Q(+) and Q(−) in which the respective currents Ip are temporally integrated is a charge amount accumulated in the stabilization capacitance 103. Thus,ΔVc=[Q(+)−Q(−)]/Cp corresponds to the voltage variation in the voltage Vp2.
FIG. 7 shows the result of the SPICE simulation similarly to FIG. 6 and shows the variation in the voltage Vp2 when the write operation is carried out 1000 times at a speed of 100 MHz. The voltage level Vp1 is assumed to be 675 mV. Because of the coupling of the parasitic capacitance Cc, the voltage Vp2 varies by about 7 mV for each write operation. However, this variation is not a problem because this is equal every time. On the other hand, the level of the voltage Vp2 is known to vary by about 2 mV in the long term because of the foregoing accumulation effect. In short, the voltage variation of about 2 mV is generated from the time immediately after the start of the write to the time of the completion (ΔVc≈2 mV). As shown in FIG. 4, even in case of the voltage variation of several mV, there is a risk that the write current variation of several % is caused. This leads to an erroneous operation at the time of write and results in reduction in the reliability of the MRAM.
As mentioned above, the related-art semiconductor integrated circuit has the difficulty that the influence of the coupling of the parasitic capacitance causes the internal voltage from the voltage generating circuit 101 to be greatly varied in the long term. This leads to the erroneous operation of the function circuit 102 that operates in accordance with the internal voltage. Also, when the operation of the function circuit 102 is kept waiting until the internal voltage is stabilized (until Vp2=Vp1 in the foregoing example), the entire operation speed of the semiconductor integrated circuit is decreased. This acts as a factor that prevents the higher speed operation of the MRAM.